Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
multipliers versus adders, a 16 x 16 radix-4 Booth multiplier and a 16-bit ripple carry adder were implemented in Verilog. Using 1, 000 ... was carried out. The results show that in the 16-bit case, the paper is implemented with adders only. ... There are also a set of interleaved modulo-8 counters (N_buff_A_r and N buff B r) .
| Title | : | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
| Author | : | |
| Publisher | : | - 2007 |
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