Finite State Machine Datapath Design, Optimization, and Implementation

Finite State Machine Datapath Design, Optimization, and Implementation

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Finite State Machine-Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, dual-ports, and register files are examined. Finally, design issues regarding cooperating Finite State Machine/Datapaths are explored. All design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.Justin S. Davis, Justin Davis, Robert Bryan Reese. output dataset contains Cnew. The latency of a datapath measures the number of clock cycles required for a calculation on an input dataset and this number is from the first element of theanbsp;...


Title:Finite State Machine Datapath Design, Optimization, and Implementation
Author: Justin S. Davis, Justin Davis, Robert Bryan Reese
Publisher:Morgan & Claypool Publishers - 2008
ISBN-13:

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